On Monday July 1 at 14:00 we have the pleasure to welcome Kevin Garello from Imec, Belgium. He will give us a seminar at CEA/IRIG, Bat 1005, room 445 entitled :
SOT-MRAM: from fundamentals to large scale technology integration
Microelectronics industry is facing major challenges related to the volatility of CMOS cache memory elements (usually SRAM and eDRAM). Due to decreasing devices size, leakage current in standby mode are now dominating the power dissipation of CMOS circuits. Furthermore, the increased density and reduction in die area lead to heat dissipation and reliability issues. Magnetic RAM (MRAMs) and Spin-Transfer-Torque MRAM (STT-MRAM[1]) are among most credible non-volatile memories candidates that are scalable, low power and with relatively low access times, as well as a compatibility with scaled CMOS processes and voltages. In fact, past years have seen major foundries and tool suppliers investing significant R&D resources into embedded STT-MRAM. They recently started prototyping demonstrators, progressively maturing for mass production for embedded memories. Despite all these advantages, STT-MRAM also faces several challenges: i. the write process is still relatively inefficient and long compared to SRAM, ii. speed gain requires to increase current flowing through the bit cell – magnetic tunnel junction (MTJ) – which imposes a severe stress and leads to a reduced endurance of the device and increased error rates. Today, this limits the use of STT-MRAM for eFlash and MCU replacements in caches memories.
Spin-Orbit Torque (SOT)[2] is an alternative spin current source originating from the spin-orbit interaction and mediated by Spin Hall and Rashba effects. SOT distinguishes by offering the possibility to switch magnetization using in-plane currents, unlike STT that requires a current flow in the perpendicular direction through MTJ. Such new memory class, SOT-MRAM[3,4], promise to mitigate some of the above issues: it is a three terminal MTJ-based concept that allows isolating the read and the write path. It results in significant improvement of the read stability, the write speed and the endurance of the device; therefore opening the path to address SRAM replacement in lowest cache level by MRAM.
Across the presentation, I will present our recent development to build and integrate SOT-MTJ cells following industrial processes, using Imec’s 300mm platform. After reviewing some key physics involved and material developments, I will describe our first successful integration scheme of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes[5]. In a second part I will introduce our recent breakthrough field-free switching SOT-MRAM concept[6] that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties, opening a new area for MRAM (SOT, STT and VCMA) technology development. Finally, I will discuss some of our recent progress to bring SOT-MRAM toward industrial compatibility.
[1] C. Chappert et. al, The emergence of spin electronics in data storage, Nature Materials 6, 813–823 (2007)
[2] I. M. Miron, et. al, Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection , Nature 476, 189 (2011)
[3] M. Cubukcu, et al., Spin-orbit torque magnetization switching of a three-terminal perpendicular magnetic tunnel junction, Appl. Phys. Lett. 104, 042406 (2014)
[4] G. Prenat et. al, Ultra-fast and high-reliability SOT-MRAM: From cache replacement to normally-Off computing, IEEE Trans. on Multi-Scale Computing Systems 2 (1), 49-60 (2015)
[5] K. Garello et. al, IEEE Symposium on VLSI Circuit, 81-82 (2018)
[6] K. Garello et. al, VLSI 2019 proceedings (2019)
