Overview
The Magnetic Random Access Memories (MRAM) group develops advanced concepts in this emerging technology. The goal is to realize cells with improved thermal stability, lower power consumption and/or faster switching. Our research covers material stack deposition, nano-fabrication and electrical test evaluation, for applications as standalone memory and non-volatile logic and more recently in neuromorphic computing architectures.
Research directions
Perpendicular Anisotropy Materials
High energy barriers for spin transfer torque (STT) MRAM cells can be achieved with perpendicular anisotropy magnetic tunnel junctions. Solutions for high density MRAM cells to diameters below 20nm require continuous improvements in perpendicular surface anisotropy, while maintaining high TMR properties.
Perpendicular STT MRAM
Evaluation of MRAM concepts requires simulation of expected reversal mechanisms and electrical characterization of individual cells. We aim at understanding dynamics of magnetization reversal and the expected impact of stack modifications to explore application specific optimizations.
Nanofabrication Challenges
Innovation on dense MRAM using pre-patterned substrates, CMOS integration of multifunctional cells and sub-10nm lateral sizes. Tunnel junction nanofabrication in our platform is essential to evaluate MRAM concepts and performance.
Perpendicular Shape Anisotropy
A solution for sub-10nm cell sizes uses high aspect ratios to generate perpendicular shape anisotropy providing scalable retention at the smallest cell sizes. Spin transfer torque switching is possible in these cells, where the reversal dynamics is now under study.
The team
Former members
Post-docs
- Andrey TIMOPHEEV (2014-2017)
- Van Dai NGUYEN (2016-2018)
- J. Ranier Roiz (2015-2016)
- Nikita Strelkov (2016-2019)
PhD
- Luc TILLIE (2015-2018)
- Nicolas PERRISSIN (2015-2018)
- Jyotirmoy CHATTERGEE (2014-2017)
- Hieu Tan NGUYEN (2013-2016)
- Antoine Chavent (2013-2015)
Process Engineers
- Jude GUELFFUCCI (2015-2017)
- Nathalie LAMARD (2016-2017)
- Guillaume LAVAITTE (2015-2016)
Projects
- Samsung SGMI (2014-2017)
- ANR Excalyb (2014-2017)
- Heumem (2015-2018)
- EU-FET Spice (2016-2019)
- EU Great (2016-2019)
- ERC Magical (2015-2020)
Partners
- CEA LETI, Grenoble, France
- Institut NEEL, Grenoble, France
- Crocus Technology, Grenoble, France
- Samsung, San Jose, USA
- Singulus AG, Kahl am Main, Germany
- Aarhus University, Aarhus, Denmark
- Radboud Universiteit, Neijmegen, Netherlands
Recent news
- Une mémoire STT MRAM sub-nanoseconde made in Spintec (December 09th, 2015)
Spintec développe une mémoire STT-MRAM dix fois plus rapide que les produits annoncés pour 2016 chez Samsung ou Intel. Sa vitesse d’écriture est inférieure à la nanoseconde, contre 5 à 10 nanosecondes habituellement. La différence ... - Améliorer le contrôle de l’écriture sub-nanoseconde de mémoires magnétiques en augmentant le rapport de forme des cellules mémoires (October 07th, 2015)
Les mémoires magnétiques à base de jonctions tunnel magnétiques appelées Spin-Transfer-Torque Random Access Memories (STT-MRAM) suscitent un intérêt considérable pour la micro-électronique grâce à leurs avantages combinés de non-volatilité, densité, vitesse, endurance. Dans ce travail, ... - WP6 : BENCHMARKING AND ROADMAP FOR HYBRID NON-VOLATILE LOGIC CMOS/MTJ TECHNOLOGY (July 02nd, 2015)
The purpose of this WP is twofold. The first purpose is benchmark the performance of these CMOS/MTJ based circuits with those of CMOS-only circuits of similar functionalities. This work is still in progress but some initial ... - WP5 : FABRICATION AND TEST OF HYBRID CMOS/MTJ CIRCUITS (July 02nd, 2015)
For the fabrication of CMOS/MTJ circuits, three different technological lines were developed and made accessible for HYMAGINE purposes. For simple circuits comprising only a few MTJs interconnected with CMOS transistors, the PTA 400m² upstream research clean-room ... - WP4 : DESIGN OF LOW-POWER HYBRID CMOS/MAGNETIC CIRCUITS (July 02nd, 2015)
Within HYMAGINE, circuits of increasing complexity have been conceived from simple non-volatile logic gates to microcontrollers or microprocessor. Below is an example of magnetic Look-Up-Table (MLUT) conceived within HYMAGINE and an example of hybrid CMOS/MTJmicroprocessor. Magnetic LUT ...
