Overview
The Magnetic Random Access Memories (MRAM) group develops advanced concepts in this emerging technology. The goal is to realize cells with improved thermal stability, lower power consumption and/or faster switching. Our research covers material stack deposition, nano-fabrication and electrical test evaluation, for applications as standalone memory and non-volatile logic and more recently in neuromorphic computing architectures.
Research directions
Perpendicular Anisotropy Materials
High energy barriers for spin transfer torque (STT) MRAM cells can be achieved with perpendicular anisotropy magnetic tunnel junctions. Solutions for high density MRAM cells to diameters below 20nm require continuous improvements in perpendicular surface anisotropy, while maintaining high TMR properties.
Perpendicular STT MRAM
Evaluation of MRAM concepts requires simulation of expected reversal mechanisms and electrical characterization of individual cells. We aim at understanding dynamics of magnetization reversal and the expected impact of stack modifications to explore application specific optimizations.
Nanofabrication Challenges
Innovation on dense MRAM using pre-patterned substrates, CMOS integration of multifunctional cells and sub-10nm lateral sizes. Tunnel junction nanofabrication in our platform is essential to evaluate MRAM concepts and performance.
Perpendicular Shape Anisotropy
A solution for sub-10nm cell sizes uses high aspect ratios to generate perpendicular shape anisotropy providing scalable retention at the smallest cell sizes. Spin transfer torque switching is possible in these cells, where the reversal dynamics is now under study.
The team
Former members
Post-docs
- Andrey TIMOPHEEV (2014-2017)
- Van Dai NGUYEN (2016-2018)
- J. Ranier Roiz (2015-2016)
- Nikita Strelkov (2016-2019)
PhD
- Luc TILLIE (2015-2018)
- Nicolas PERRISSIN (2015-2018)
- Jyotirmoy CHATTERGEE (2014-2017)
- Hieu Tan NGUYEN (2013-2016)
- Antoine Chavent (2013-2015)
Process Engineers
- Jude GUELFFUCCI (2015-2017)
- Nathalie LAMARD (2016-2017)
- Guillaume LAVAITTE (2015-2016)
Projects
- Samsung SGMI (2014-2017)
- ANR Excalyb (2014-2017)
- Heumem (2015-2018)
- EU-FET Spice (2016-2019)
- EU Great (2016-2019)
- ERC Magical (2015-2020)
Partners
- CEA LETI, Grenoble, France
- Institut NEEL, Grenoble, France
- Crocus Technology, Grenoble, France
- Samsung, San Jose, USA
- Singulus AG, Kahl am Main, Germany
- Aarhus University, Aarhus, Denmark
- Radboud Universiteit, Neijmegen, Netherlands
Recent news
- A dipolar core-shell perpendicular shape anisotropy memory cell (July 08th, 2024)
We propose the concept of a core-shell composite structure coupled antiparallel via dipolar interaction, as the storage layer in perpendicular-shape-anisotropy magnetic random access memory (PSA MRAM). Benefits compared with a standard PSA MRAM include a ... - PhD position – Spin transfer torque magnetic field sensing (June 14th, 2024)
Topic PhD scholarship to work on a novel sensing approach exploring spin transfer torque (STT) for magnetic field sensing in perpendicular anisotropy magnetic tunnel junctions. The project aims at high-density low power consumption sensors, departing from ... - Seminar – Ten Years of 2D Materials based Spintronics Research: Highlights and Future (April 15th, 2024)
On Tuesday May 14, 2024 at 14:00 we have the pleasure to welcome Prof. Stephan ROCHE (ICREA, Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC, BIST). He will give us a seminar entitled: Ten Years of ... - Portrait – Louis Farcis, doctorant à SPINTEC (February 13th, 2024)
Louis Farcis est chercheur doctoral à SPINTEC. Son travail concerne les architectures non-conventionnelles pour réaliser des calculs à base de réseaux de neurones spintroniques. Son portrait a été réalisé par l’Institut de Recherche Interdisciplinaire de ... - Resistively-coupled stochastic MTJ for energy-based optimum search (January 22nd, 2024)
We study recurrent networks of binary stochastic Magnetic Tunnel Junctions (sMTJ), aiming at efficiently solving computationally hard optimization problems. After validating a prototyping route, we investigate the impact of hybrid CMOS+MTJ building block variants on ...