Context: The last decade has seen the emergence of numerous studies around integrated nanoelectronic technologies for a growing number of application areas, ranging from the Internet of Things, to integrated components specialized in the management and optimization of energy consumption, environmental monitoring, safety and security in the automotive and space industries, support and control in the healthcare field, and hardware implementations of Artificial Intelligence (AI) algorithms. Today’s mature and emerging nanoelectronic technologies present a lot of challenges for the design, validation and test of digital and mixed-signal circuits and architectures. A particular attention is given to memory design. Actually, due to the increase in computing capacity, a proportional increase in the amount of data to be processed is observed in SoCs, thus creating larger memory capacity requirements. The latest technologies make these memories denser and thus defects due to the manufacturing process are more prone to occur not only in the memory array but also in the periphery of the memory. Memory test is currently based on the use of March algorithms targeting Functional Fault Models (FFMs). However, with shrinking technologies, these solutions will shortly become insufficient to achieve high coverage of new defect types that may occur during the manufacturing process. One solution to this problem is to adapt Cell-Aware (CA) test concepts successfully developed and fully deployed for logic circuits to emerging non-volatile (i.e., STT-MRAM and SOT-MRAM) memory technologies. CA test assumes that many escapes during testing are due to defects within standard cells. CA test uses a cell-internal-fault dictionary (called CA model) describing the detection conditions of each potential defect affecting a standard cell.
By adapting innovations from the digital world to memory testing, and by replacing functional testing of MRAM memories by structural testing, this project will satisfy two objectives: i) anticipate the widening gap between correct functional modeling and realistic behavior of defects in memories, and ii) consider new failure mechanisms in MRAM technologies that cannot always be modeled by FFMs and thus be targeted by nowadays test procedures.
Objectives: The goal of the post-doctoral position is hence to develop test characterization models (i.e., CA models) for the gate-cells (elementary cells, simple and complex logic gates) extracted from the description of MRAM memory circuit description. These models will be enriched with layout information to allow complete coverage of realistic defects during test and diagnosis processes. Considering the significant number and the diversity of gate-cells for all considered memory technologies, Machine Learning techniques will be used for the automated generation process of these models in a time-efficient manner. Once the test characterization models will be generated, they will be used through new algorithms, that should be developed, to improve the test and diagnostic quality.
Keywords: Memories, MRAM, Defect, Characterization models, Test, Diagnosis, Quality, Machine Learning
Starting date / duration: June 2024 / 18 months
Required skills: The applicant must have a PhD degree in Microelectronics and/or Nanoelectronics, with skills in the fields of digital circuit design, and good knowledge of programming languages (Python, Matlab, etc.)
Funding and partners: The post doctoral contract will be funded by the ANR (French National Research Agency) in the framework of the « QUALMEM » ANR project selected in 2022. The work will be done in collaboration between LIRMM (UMR 5506 Université de Montpellier / CNRS), SPINTEC (UMR 8191 CEA / CNRS / Université Grenoble-Alpes / Grenoble INP) and STMicroelectronics (Crolles).
Contact: Lorena ANGHEL, Full Professor, lorena.anghel@phelma.grenoble-inp.fr , Tel. +33 (0) 4 38 78 44 16