Overview GREAT (European H2020 project) was accepted at the Summer 2015. Its kick-off meeting took place at SPINTEC in Grenoble on February 22nd-23rd 2016. The project aims at developing magnetic stacks able to equally perform memory, radio-frequency as well as sensor functionalities on the same chip, to address Internet of Things (IoT) applications. The main objectives of […]

A new research project has been accepted at the last FET H2020 call. The objective of SPICE is to realize a novel integration platform that combines photonic, magnetic and electronic components. Its validity will be shown by a conceptually new spintronic-photonic memory chip demonstrator with three orders of magnitude faster write speed and two orders […]

Jeudi 21 Janvier 2016 à 14H00, Phelma MINATEC – Amphithéâtre M001 (3 Parvis Louis Néel – 38016 Grenoble) Monsieur Antoine CHAVENT du DSM/INAC/SPINTEC soutiendra une thèse intitulée « Réduction du champ d’écriture de mémoires magnétiques à écriture assistée thermiquement à l’aide du couple de transfert de spin » Les mémoires magnétiques à accès aléatoire (MRAM) développées par […]

During writing of Thermally Assisted Switching Magnetic Random Access Memory (TAS-MRAM), the torque due to a voltage pulse may be used to help writing. As part of collaboration between Spintec and Crocus Technology, we brought out that most of the influence of the spin transfer torque is exerted during the last part of the voltage […]

Spintec développe une mémoire STT-MRAM dix fois plus rapide que les produits annoncés pour 2016 chez Samsung ou Intel. Sa vitesse d’écriture est inférieure à la nanoseconde, contre 5 à 10 nanosecondes habituellement. La différence tient au processus de déclenchement du pulse d’écriture. Spintec l’accélère grâce à deux polariseurs d’aimantation orthogonale, placés de part et […]

Les mémoires magnétiques à base de jonctions tunnel magnétiques appelées Spin-Transfer-Torque Random Access Memories (STT-MRAM) suscitent un intérêt considérable pour la micro-électronique grâce à leurs avantages combinés de non-volatilité, densité, vitesse, endurance. Dans ce travail, une nouvelle variété de telles mémoires a été développée offrant une vitesse d’écriture sub-ns appropriée pour les applications de type […]

The purpose of this WP is twofold. The first purpose is benchmark the performance of these CMOS/MTJ based circuits with those of CMOS-only circuits of similar functionalities. This work is still in progress but some initial results on CMOS/MTJ based microprocessor derived from RISK processor have already been obtained in WP4: Design of low-power hybrid […]

For the fabrication of CMOS/MTJ circuits, three different technological lines were developed and made accessible for HYMAGINE purposes. For simple circuits comprising only a few MTJs interconnected with CMOS transistors, the PTA 400m² upstream research clean-room located in SPINTEC building is used. A MRAM back-end process is operational at PTA and specific process steps required […]

Within HYMAGINE, circuits of increasing complexity have been conceived from simple non-volatile logic gates to microcontrollers or microprocessor. Below is an example of magnetic Look-Up-Table (MLUT) conceived within HYMAGINE and an example of hybrid CMOS/MTJmicroprocessor. Magnetic LUT for FPGA Our purpose was to develop a radiation-hardened FPGA based on MRAM. A FPGA (Field Programmable Gate […]

Thanks to their unique set of assets (non-volatility, speed, density, endurance), STT-MRAM are seen as a unique candidate for DRAM and/or Cache SRAM replacement allowing to drastically reduce the power consumption of electronic circuits thanks to new power gating strategies made possible by the non-volatility of these memories. For these applications, fast write speed (in […]