On the 20th of may, 2016, we have the pleasure to welcome in Spintec Michael Gaidis from Samsung, San Jose.

At 11H, he will give a talk lecture in room 446, building 10.05 entitled ““Scaling STT-MRAM:  why, how, and when?”
STT-MRAM Scaling Overview:  Why/How/When?

Michael Gaidis, Samsung device solution, San Jose, California

The presentation will give an overview of the main drivers for STT-MRAM scaling, and the major reasons why it may not live up to the hype that many have associated with it.  The relevant fabrication practices used for scaling STT-MRAM will be reviewed.  Finally, predictions will be made for when STT-MRAM will achieve widespread use, and in what applications.

Biography

Michael Gaidis is a Senior Manager with Samsung Device Solutions in San Jose, California, focused on strategy, university relationships, and startup funding in the fields of memory and storage and emerging IoT.

Michael works closely with the Memory Solutions Lab (flash, DRAM, memory systems), the Device Lab (modeling of advanced logic and memory devices), the New Memory Technology Lab (MRAM), and the Samsung Strategy and Innovation Center (SSIC).

He has previously worked as a device physicist, with research including resistive RAM, MRAM, plasmonics, and terahertz and x-ray sensor devices and spaceflight systems.  Michael has spent the majority of his career working at IBM’s TJ Watson Research Center and NASA’s Jet Propulsion Lab.

His education included a postdoctoral fellowship in physics and astronomy at Caltech, a PhD in applied physics at Yale, and MS/BS degrees in EE, CS, and physics at MIT.