MAGNETIC LOGIC FUNCTIONALITIES AND SCALABILITY OF THERMALLY ASSISTED MRAMS

I.L. Prejbeanu, R.C. Sousa, B. Dieny, J.-P. Nozieres, S. Bandiera, K. Mackay

On paper, MRAMs combine non volatility, high speed, moderate power consumption, infinite endurance and radiation hardness, all at low cost and easy to embed. Since its inception in the late 90’s, however, and despite numerous promising announcements from laboratories, large corporations and start-ups, MRAM has failed to live to its expectations. Large volume applications are still to be seen, with only Toggle switching-based standalone products currently available, at 180nm technology node. The recent advent of spin transfer torque, however, has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology node. As a consequence, MRAM is now viewed again as a credible replacement to existing technologies for applications where the combination of non-volatility, speed, low power and endurance is key.

A recent report from ITRS ERD/ERM working group has identified STT MRAM and Redox RAM as the most promising candidates for emerging scalable and manufacturable non-volatile memories. In this paper, we show how thermal assistance [1] can be implemented in field induced switched MTJ to enhance the reliability, the power consumption and the scalability of MRAM. A new self-referenced reading scheme can be implemented in such MTJ in order to obtain a Magnetic Logic Unit (MLUTM) that present new logic functionalities compared to standard MRAM. In a second time, we will present the implementation of thermal assistance in MTJ with current induced switching writing scheme. In that case, no field line is required, increasing thus the storage capacity of MRAM cell and decreasing the writing consumption while keeping a satisfying data retention capacity. Ultimately, thermal assistance can be implemented in MTJ with perpendicular magnetization [2]. In that case, thermally induced anisotropy reorientation (TIAR) can be used to decrease the switching power consumption, increase the writing reliability and improve further the scalability of TA-MRAM down to 22nm technological node.

[1] I.L. Prejbeanu et al, J. of Phys: Cond. Matter 19 165218 (2007)

[2] S. Bandiera et al, Appl. Phys. Lett. 99 202507 (2011)

 


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